1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly to a test method for testing, for example, a semiconductor memory.
2. Description of the Related Art
In accordance with increases in the scale of large scale integrated circuits (LSIs), it is becoming difficult to test the circuits during development or manufacturing. Therefore, LSI testing techniques are becoming more and more important.
In conventional LSI function tests, it is determined whether an LSI is faulty by inputting test patterns to the input terminals of the LSI and checking whether the data from the output terminals is as expected. Further, in accordance with the increase in structural complexity of LSIs, designs for testability have been developed. As designs for testability, a scan design method, a method incorporating a built-in self-test (BIST), etc., are widely known. Concerning designs for testability, see, for example, “Design for AT-SPRRD Test, Diagnosis and Measurement”, Chapter 2, pp. 35–57, by Benoit Nadeau-Dostie, published by Kluwer Academic Publishers in 2000.
However, in accordance with recent increases in LSI scale and operation frequency, it has become difficult for conventional test methods to guarantee the operation of LSIs. For example, since the structure of LSIs has become very complex, a large number of test patterns must be input to them, which requires considerable time and expense. Also in the method of incorporating a BIST circuit, the testing costs and time are increased because the operations of LSIs are very complex.